{"database":"biostudies-literature","file_versions":[],"scores":null,"additional":{"submitter":["Liao F"],"funding":["National Natural Science Foundation of China (National Science Foundation of China)"],"pagination":["10932"],"full_dataset_link":["https://www.ebi.ac.uk/biostudies/studies/S-EPMC12686015"],"repository":["biostudies-literature"],"omics_type":["Unknown"],"volume":["16(1)"],"pubmed_abstract":["An architecture for three-dimensional integration of dynamic random-access memory that enables higher memory density is presented as a new solution to the bottleneck currently faced in artificial intelligence deployment. The basis of this architecture is a vertical dual-gate two-transistors-zero-capacitor memory cell which yields a small feature size and reliable read operation, and naturally scalable to large-scale arrays. However, three-dimensional integration of the dynamic random-access memory faces highly-limiting challenges related to lateral misalignment and thermal cycling as a result of separate stacking processes. To solve the issues of cell misalignment and thermal cycling, a single step process is used to stack the dual-gate In-Ga-Zn-O transistors simultaneously. By optimizing "],"journal":["Nature communications"],"pubmed_title":["High-density three-dimensional integration of dynamic random-access memory using vertical dual-gate IGZO TFTs."],"pmcid":["PMC12686015"],"funding_grant_id":["62488201","62574003"],"pubmed_authors":["Mao N","Wang GL","Zhu Z","Lu W","Liu M","Zhang J","Wang J","Yue J","Wang L","Wu Z","Liao F","Jin M","Yu Y","Yang G","Wu XS","Chen K","Zhao C","Nathan A","Lu C","Kang BM","Li L","Geng D","Li Z","Lu N","Zhang X","Liu C","Shi J"],"additional_accession":[]},"is_claimable":false,"name":"High-density three-dimensional integration of dynamic random-access memory using vertical dual-gate IGZO TFTs.","description":"An architecture for three-dimensional integration of dynamic random-access memory that enables higher memory density is presented as a new solution to the bottleneck currently faced in artificial intelligence deployment. The basis of this architecture is a vertical dual-gate two-transistors-zero-capacitor memory cell which yields a small feature size and reliable read operation, and naturally scalable to large-scale arrays. However, three-dimensional integration of the dynamic random-access memory faces highly-limiting challenges related to lateral misalignment and thermal cycling as a result of separate stacking processes. To solve the issues of cell misalignment and thermal cycling, a single step process is used to stack the dual-gate In-Ga-Zn-O transistors simultaneously. By optimizing ","dates":{"release":"2025-01-01T00:00:00Z","publication":"2025 Dec","modification":"2026-06-05T23:44:40.187Z","creation":"2026-05-23T03:13:42.664Z"},"accession":"S-EPMC12686015","cross_references":{"pubmed":["41360784"],"doi":["10.1038/s41467-025-65925-3"]}}