biostudies-literatureLiao FNational Natural Science Foundation of China (National Science Foundation of China)10932https://www.ebi.ac.uk/biostudies/studies/S-EPMC12686015biostudies-literatureUnknown16(1)An architecture for three-dimensional integration of dynamic random-access memory that enables higher memory density is presented as a new solution to the bottleneck currently faced in artificial intelligence deployment. The basis of this architecture is a vertical dual-gate two-transistors-zero-capacitor memory cell which yields a small feature size and reliable read operation, and naturally scalable to large-scale arrays. However, three-dimensional integration of the dynamic random-access memory faces highly-limiting challenges related to lateral misalignment and thermal cycling as a result of separate stacking processes. To solve the issues of cell misalignment and thermal cycling, a single step process is used to stack the dual-gate In-Ga-Zn-O transistors simultaneously. By optimizing Nature communicationsHigh-density three-dimensional integration of dynamic random-access memory using vertical dual-gate IGZO TFTs.PMC126860156248820162574003Mao NWang GLZhu ZLu WLiu MZhang JWang JYue JWang LWu ZLiao FJin MYu YYang GWu XSChen KZhao CNathan ALu CKang BMLi LGeng DLi ZLu NZhang XLiu CShi JfalseHigh-density three-dimensional integration of dynamic random-access memory using vertical dual-gate IGZO TFTs.An architecture for three-dimensional integration of dynamic random-access memory that enables higher memory density is presented as a new solution to the bottleneck currently faced in artificial intelligence deployment. The basis of this architecture is a vertical dual-gate two-transistors-zero-capacitor memory cell which yields a small feature size and reliable read operation, and naturally scalable to large-scale arrays. However, three-dimensional integration of the dynamic random-access memory faces highly-limiting challenges related to lateral misalignment and thermal cycling as a result of separate stacking processes. To solve the issues of cell misalignment and thermal cycling, a single step process is used to stack the dual-gate In-Ga-Zn-O transistors simultaneously. By optimizing 2025-01-01T00:00:00Z2025 Dec2026-06-05T23:44:40.187Z2026-05-23T03:13:42.664ZS-EPMC126860154136078410.1038/s41467-025-65925-3