A reconfigurable binary/ternary logic conversion-in-memory based on drain-aligned floating-gate heterojunction transistors.

ABSTRACT: A new type of heterojunction non-volatile memory transistor (H-MTR) has been developed, in which the negative transconductance (NTC) characteristics can be controlled systematically by a drain-aligned floating gate. In the H-MTR, a reliable transition between N-shaped transfer curves with distinct NTC and monolithically current-increasing transfer curves without apparent NTC can be accomplished through programming operation. Based on the H-MTR, a binary/ternary reconfigurable logic inverter (R-inverter) has been successfully implemented, which showed an unprecedentedly high static noise margin of 85% for binary logic operation and 59% for ternary logic operation, as well as long-term stability and outstanding cycle endurance. Furthermore, a ternary/binary dynamic logic conversion-in-memory

SUBMITTER: Lee C 

PROVIDER: S-EPMC10290076 | biostudies-literature | 2023 Jun

REPOSITORIES: biostudies-literature