Silicon-van der Waals heterointegration for CMOS-compatible logic-in-memory design.

ABSTRACT: Silicon CMOS-based computing-in-memory encounters design and power challenges, especially in logic-in-memory scenarios requiring nonvolatility and reconfigurability. Here, we report a universal design for nonvolatile reconfigurable devices featuring a 2D/3D heterointegrated configuration. By leveraging the photo-controlled charge trapping/detrapping process and the partially top-gated energy band landscape, the van der Waals heterostacking achieves polarity storage and logic reconfigurable characteristics, respectively. Precise polarity tunability, logic nonvolatility, robustness against high temperature (at 85°C), and near-ideal subthreshold swing (80 mV dec-1) can be done. A comprehensive investigation of dynamic charge fluctuations provides a holistic understanding of the origins of non

SUBMITTER: Lee MP 

PROVIDER: S-EPMC10708197 | biostudies-literature | 2023 Dec

REPOSITORIES: biostudies-literature