High-density vertical sidewall MoS₂ transistors through T-shape vertical lamination.

ABSTRACT: Vertical transistors, in which the source and drain are aligned vertically and the current flow is normal to the wafer surface, have attracted considerable attention recently. However, the realization of high-density vertical transistors is challenging, and could be largely attributed to the incompatibility between vertical structures and conventional lateral fabrication processes. Here we report a T-shape lamination approach for realizing high-density vertical sidewall transistors, where lateral transistors could be pre-fabricated on planar substrates first and then laminated onto vertical substrates using T-shape stamps, hence overcoming the incompatibility between planar processes and vertical structures. Based on this technique, we vertically stacked 60 MoS₂ transistors with

SUBMITTER: Tao Q 

PROVIDER: S-EPMC11233715 | biostudies-literature | 2024 Jul

REPOSITORIES: biostudies-literature