System-level modeling with temperature compensation for a CMOS-MEMS monolithic calorimetric flow sensing SoC.

ABSTRACT: We present a system-level model with an on-chip temperature compensation technique for a CMOS-MEMS monolithic calorimetric flow sensing SoC. The model encompasses mechanical, thermal, and electrical domains to facilitate the co-design of a MEMS sensor and CMOS interface circuits on the EDA platform. The compensation strategy is implemented on-chip with a variable temperature difference heating circuit. Results show that the linear programming for the low-temperature drift in the SoC output is characterized by a compensation resistor R_c with a resistance value of 748.21 Ω and a temperature coefficient of resistance of 3.037 × 10^-3 °C^-1 at 25 °C. Experimental validation demonstrates that within an ambient temperature range of 0-50 °C and a flow range of 0-10 

SUBMITTER: Hong L 

PROVIDER: S-EPMC11743593 | biostudies-literature | 2025 Jan

REPOSITORIES: biostudies-literature