Electrolyte-Gated Transistor Array (20 × 20) with Low-Programming Interference Based on Coplanar Gate Structure for Unsupervised Learning.

ABSTRACT: Compute-in-memory (CIM) is a pioneering approach using parallel data processing to eliminate traditional data transmission bottlenecks for faster, energy-efficient data handling. Crossbar arrays with two-terminal devices such as memristors and phase-change memory are commonly employed in CIM, but they encounter challenges such as leakage current and increased power usage. Three-terminal transistor arrays have potential solutions, yet large-scale electrolyte-gated transistors (EGTs) demonstrations are uncommon due to compatibility issues with existing photolithography processes. Herein, a 20 × 20 EGTs array is designed using indium-gallium-zinc-oxide as the semiconductor channel and polyacrylonitrile (PAN) doped with C₂F₆LiNO₄S₂ as the electrolyte

SUBMITTER: Zhang W 

PROVIDER: S-EPMC11935182 | biostudies-literature | 2024 Apr

REPOSITORIES: biostudies-literature