Structurally optimized SiC CMOS FinFET for high-temperature and low-power SoC logic integration.

ABSTRACT: A high-temperature-operable binary inverter was designed through structural optimization of SiC-based CMOS FinFETs using 3D TCAD simulations. A FinFET architecture was incorporated into SiC CMOS with an optimized fin structure to overcome the critical challenges of high subthreshold swing (SS) and threshold voltage (V_th) inherent in planar MOSFET-based SiC CMOS technology, thus achieving a high-performance logic system. Subsequent structural optimization led to V_th values of 1.83 and 2.54 V for the n-type and p-type FinFETs, respectively, along with substantially enhanced SS values of 73.33 and 77.74 mV/decade, respectively. Additionally, to validate the applicability of SiC CMOS FinFETs to high-temperature environments compared to conventional Si CMOS FinFETs, the se

SUBMITTER: Kwon TS 

PROVIDER: S-EPMC12317143 | biostudies-literature | 2025 Aug

REPOSITORIES: biostudies-literature