Scalable Inter-Dielectric Engineering via Vapor-Phase Synthesis Process for Top-Gate MoS₂ Thin-Film Transistor.

ABSTRACT: 2D semiconductors are promising channel materials for next-generation thin-film transistors (TFTs) in Internet of Things (IoT) devices. However, their inert, dangling-bond-free surfaces make uniform high-k dielectric integration challenging and can lead to interface defect formation. Here, a scalable inter-dielectric engineering strategy is introduced to address this challenge, using initiated chemical vapor deposition (iCVD) to deposit an ultrathin nonpolar poly(1,3,5-trimethyl-1,3,5-trivinylcyclotrisiloxane) (pV3D3) film as an interlayer between MoS₂ and HfO₂. This pV3D3 buffer layer forms uniformly without pinholes or clusters on MoS₂, yielding excellent interface quality and effectively suppressing HfO₂-induced uncontrollable doping effect an

SUBMITTER: Park S 

PROVIDER: S-EPMC12548015 | biostudies-literature | 2025 Oct

REPOSITORIES: biostudies-literature