Middle Interlayer Engineered Ferroelectric NAND Flash Overcoming Reliability and Stability Bottlenecks for Next-Generation High-Density Storage Systems.

ABSTRACT: Multilevel storage and low-voltage operation position ferroelectric transistors as promising candidates for next-generation nonvolatile memory. Among them, gate-injection-type ferroelectric transistors offer improved vertical scalability and power efficiency for three-dimensional (3D) NAND flash. However, their intricate interplay between polarization switching and charge trapping complicates systematic understanding of degradation mechanisms, limiting strategies to improve reliability and stability. Here, gate stack engineering incorporating middle interlayers within HfZrO_x matrix is presented to modulate polarization dynamics, strengthening the coupling of dual mechanisms and overcoming long-standing reliability and stability bottlenecks in ferroelectric NAND operation. This a

SUBMITTER: Kim G 

PROVIDER: S-EPMC12561253 | biostudies-literature | 2025 Oct

REPOSITORIES: biostudies-literature