Low power and high-speed quadrate node upset tolerant latch design using CNTFET.

ABSTRACT: Scalability, leakage, short-channel effects, and reliability problems are some of the difficulties facing the semiconductor industry as it continues to experience a reduction in size. Heavy charged particles striking an integrated circuit (IC) cause a Single Event Upset (SEU). As devices are scaled down, it usually causes Single and Multiple Node Upset. To overcome the upsets, device and CMOS circuit radiation hardening by design (RHBD) techniques are adopted. In the resent times, Carbon nanotubes have emerged as a feasible technology capable of addressing CMOS problems while maintaining performance and reliability. This manuscript proposes a Low power High speed Quadrate Node Upset Carbon Nanotube latch (LHQCNT). The LHQCNT latch contains three Dual Interlocked cells with a delta intercon

SUBMITTER: Asiya S 

PROVIDER: S-EPMC12722330 | biostudies-literature | 2025 Dec

REPOSITORIES: biostudies-literature