Low Power, CMOS-MoS₂ Memtransistor based Neuromorphic Hybrid Architecture for Wake-Up Systems.

ABSTRACT: Neuromorphic architectures have become essential building blocks for next-generation computational systems, where intelligence is embedded directly onto low power, small area, and computationally efficient hardware devices. In such devices, realization of neural algorithms requires storage of weights in digital memories, which is a bottleneck in terms of power and area. We hereby propose a biologically inspired low power, hybrid architectural framework for wake-up systems. This architecture utilizes our novel high-performance, ultra-low power molybdenum disulphide (MoS₂) based two-dimensional synaptic memtransistor as an analogue memory. Furthermore, it exploits random device mismatches to implement the population coding scheme. Power consumption per CMOS neuron block was found

SUBMITTER: Gupta S 

PROVIDER: S-EPMC6821695 | biostudies-literature | 2019 Oct

REPOSITORIES: biostudies-literature