CMOS-compatible ferroelectric NAND flash memory for high-density, low-power, and high-speed three-dimensional memory.

ABSTRACT: Ferroelectric memory has been substantially researched for several decades as its potential to obtain higher speed, lower power consumption, and longer endurance compared to conventional flash memory. Despite great deal of effort to develop ferroelectric memory based on perovskite oxides on Si, formation of unwanted interfacial layer substantially compromises the performance of the ferroelectric memory. Furthermore, three-dimensional (3D) integration has been unimaginable because of high processing temperature, non-CMOS compatibility, difficulty in scaling, and complex compositions of perovskite oxides. Here, we demonstrate a unique strategy to tackle critical issues by applying hafnia-based ferroelectrics and oxide semiconductors. Thus, it is possible to avoid the formation of interfacial

SUBMITTER: Kim MK 

PROVIDER: S-EPMC7806215 | biostudies-literature | 2021 Jan

REPOSITORIES: biostudies-literature