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Universal logic-in-memory cell enabling all basic Boolean algebra logic.

ABSTRACT: Among the promising approaches for implementing high-performance computing, reconfigurable logic gates and logic-in-memory (LIM) approaches have been drawing increased research attention. These allow for improved functional scaling of a chip, owing to the improved functionality per unit area. Although numerous studies have been conducted independently for either reconfigurable logic or LIM units, attempts to construct a hybrid structure based on reconfigurable logic and LIM units remain relatively rare. In this study, we merge reconfigurable logic gates and LIM units to achieve a universal logic-in-memory (ULIM) cell for enabling all basic Boolean logic operations and data storage in a single cell. A ULIM cell consisting of silicon memory devices with reconfigurable n- and p-program modes can reconfigure logic operations within the complete set of Boolean logic operations. Moreover, the ULIM cell exhibits memory behaviors for storing output logic values without supply voltages for a certain period, resulting in zero static power consumption. Hence, this study provides a way to realize high-performance electronics by utilizing the silicon devices with a hybrid function of reconfigurable logic and LIM.

SUBMITTER: Baek E

PROVIDER: S-EPMC9684131 | biostudies-literature | 2022 Nov

REPOSITORIES: biostudies-literature

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Universal logic-in-memory cell enabling all basic Boolean algebra logic.

Baek Eunwoo E Cho Kyoungah K Kim Sangsig S

Scientific reports 20221122 1

Among the promising approaches for implementing high-performance computing, reconfigurable logic gates and logic-in-memory (LIM) approaches have been drawing increased research attention. These allow for improved functional scaling of a chip, owing to the improved functionality per unit area. Although numerous studies have been conducted independently for either reconfigurable logic or LIM units, attempts to construct a hybrid structure based on reconfigurable logic and LIM units remain relative ...[more]

PMID: 36418507

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Project description:BackgroundA key problem in the analysis of mathematical models of molecular networks is the determination of their steady states. The present paper addresses this problem for Boolean network models, an increasingly popular modeling paradigm for networks lacking detailed kinetic information. For small models, the problem can be solved by exhaustive enumeration of all state transitions. But for larger models this is not feasible, since the size of the phase space grows exponentially with the dimension of the network. The dimension of published models is growing to over 100, so that efficient methods for steady state determination are essential. Several methods have been proposed for large networks, some of them heuristic. While these methods represent a substantial improvement in scalability over exhaustive enumeration, the problem for large networks is still unsolved in general.ResultsThis paper presents an algorithm that consists of two main parts. The first is a graph theoretic reduction of the wiring diagram of the network, while preserving all information about steady states. The second part formulates the determination of all steady states of a Boolean network as a problem of finding all solutions to a system of polynomial equations over the finite number system with two elements. This problem can be solved with existing computer algebra software. This algorithm compares favorably with several existing algorithms for steady state determination. One advantage is that it is not heuristic or reliant on sampling, but rather determines algorithmically and exactly all steady states of a Boolean network. The code for the algorithm, as well as the test suite of benchmark networks, is available upon request from the corresponding author.ConclusionsThe algorithm presented in this paper reliably determines all steady states of sparse Boolean networks with up to 1000 nodes. The algorithm is effective at analyzing virtually all published models even those of moderate connectivity. The problem for large Boolean networks with high average connectivity remains an open problem.

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Universal logic-in-memory cell enabling all basic Boolean algebra logic.

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Universal logic-in-memory cell enabling all basic Boolean algebra logic.

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