Improvements in 2D p-type WSe₂ transistors towards ultimate CMOS scaling.

ABSTRACT: This paper provides comprehensive experimental analysis relating to improvements in the two-dimensional (2D) p-type metal-oxide-semiconductor (PMOS) field effect transistors (FETs) by pure van der Waals (vdW) contacts on few-layer tungsten diselenide (WSe₂) with high-k metal gate (HKMG) stacks. Our analysis shows that standard metallization techniques (e.g., e-beam evaporation at moderate pressure ~ 10^-5 torr) results in significant Fermi-level pinning, but Schottky barrier heights (SBH) remain small (< 100 meV) when using high work function metals (e.g., Pt or Pd). Temperature-dependent analysis uncovers a more dominant contribution to contact resistance from the channel access region and confirms significant improvement through less damaging metallization techniques

SUBMITTER: Patoary NH 

PROVIDER: S-EPMC9971212 | biostudies-literature | 2023 Feb

REPOSITORIES: biostudies-literature