An in-memory computing architecture based on two-dimensional semiconductors for multiply-accumulate operations.

ABSTRACT: In-memory computing may enable multiply-accumulate (MAC) operations, which are the primary calculations used in artificial intelligence (AI). Performing MAC operations with high capacity in a small area with high energy efficiency remains a challenge. In this work, we propose a circuit architecture that integrates monolayer MoS₂ transistors in a two-transistor-one-capacitor (2T-1C) configuration. In this structure, the memory portion is similar to a 1T-1C Dynamic Random Access Memory (DRAM) so that theoretically the cycling endurance and erase/write speed inherit the merits of DRAM. Besides, the ultralow leakage current of the MoS₂ transistor enables the storage of multi-level voltages on the capacitor with a long retention time. The electrical characteristics of a si

SUBMITTER: Wang Y 

PROVIDER: S-EPMC8184885 | biostudies-literature | 2021 Jun

REPOSITORIES: biostudies-literature